I’m glad to share this great talk from Prof. Dan Pitt, Executive Director from the Open Networking Foundation. In the talk, he provides a fantastic introduction to the world of Software-Defined Networks and its relationship with OpenFlow.
The NetFPGA-10G board has 4 x 10GigE SFP+ interfaces, a PCI Express interface to the host (Gen2 x8 channels), and a Xilinx Virtex-5 TX240T FPGA. The board has SRAM and DRAM (27 MBytes QDRII SRAM, 288 MBytes RLDRAM-II) and a high bandwidth expansion connector for daughter-cards.
- Xilinx Virtex-5 XC5VTX240TFFG1759 -2
- Four SFP+ interface (using 16 RocketIO GTX transceivers and 4 PHY devices)
- Supports both 10Gbps and 1Gbps modes
- X8 PCI Express Gen 2 (5Gbps/lane)
- Twenty Configurable GTX Serial Transceivers (available through two high-speed Samtec connectors)
- Three x36 QDR II (CY7C1515KV18)
- Four x32 RLDRAM II (MT49H16M36BM-25)
- Mictor Connector for debugging
- Two Platform XL Flash (128mb each)
- One Xilinx XC2C256 CPLD
- One DB9 (RS232)
- User LEDs & Push Buttons
- 9.5″ x 4.25″ board size
The current NetFPGA infrastructure release comes with reference designs that operate the NetFPGA-10G as a NIC in 1G or 10G mode with all 4 ports active. In addition, the release provides the basic building blocks of all future designs, including and PCIe endpoint with DMA, as well as software.
I’d like to share with you this nice video from Intel. The Intel Xeon Phi coprocessor: “Only” 60+ Processing Cores; common programming model across Intel® architecture; and up to 1 TERAFLOPS performance in EVERY CHIP.Based on Intel® Many Integrated Core (MIC) architecture, the Intel® Xeon Phi™ coprocessor complements the industry leading performance and energy-efficiency of the Intel® Xeon® processor E5 family to enable dramatic performance gains for some of today’s most demanding applications.http://www.youtube.com/watch?v=LIvK7BiJSPo